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mwf's avatar
mwf
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3 years ago
Solved

Arria 10 DDR4 issues

Looking for suggestions on how to proceed with a tough issue. We want to support DDR4 in future products so we added it to our board designs and FPGA pinout long before my tenure. The board design wa...
  • mwf's avatar
    mwf
    3 years ago

    I found an issue with a clock crossing boundary that should have affected both banks but yet only bank 0 failed.

    The design looks good now.

    Mike

mwf's avatar
mwf
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3 years ago

Hi Adzim. The issue has been resolved and was not a DDR4 problem but was a timing issue during write data generation.

Both interfaces appear to be working fine now.

Thanks,

Mike