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mwf's avatar
mwf
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Arria 10 DDR4 issues

Looking for suggestions on how to proceed with a tough issue. We want to support DDR4 in future products so we added it to our board designs and FPGA pinout long before my tenure. The board design wa...
  • mwf's avatar
    mwf
    3 years ago

    I found an issue with a clock crossing boundary that should have affected both banks but yet only bank 0 failed.

    The design looks good now.

    Mike

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Mike,


Thank you for submitting your question in Intel Community.


Thank you for providing your issue in details.

So now you have two identical DDR4 memory interface in a design. The Bank 0 has issue but Bank 1 is fine.


Regarding to the issue, do you see any symptom that can cause the failure? Any specific transaction that will fail?


Have you tried to test the Bank 0 alone in a design?

Like making a design with one interface only.

If that possible, can you observe the result?


Can you test the board design with EMIF example design for each interface?

Please let me know if you need help to create the design. Thank you.


Regards,

Adzim