Forum Discussion
Occasional ContributorArria 10 cannot access Transceiver ATX PLL reconfiguration interface
Hi,
i found the problem. It is hardware related:
I found it strange that the integrated processor, which takes care of the initial callibration, did not react. If I understand correctly, it is clocked by the 100 MHz user clock (clkusr). I checked the 100 MHz oscillator and well... it does not work. Since we don't use this oscillator for anything else, we didn't notice it earlier.
Thanks for the help, my problem is solved.
Regards, LFrin
Frequent ContributorHi,
In all our transceiver example designs with Nios II/NiosV We have used a custom component to access the dynamic reconfiguration interface of the transceivers called reconfig_mgmt_hw.tcl directly. So if you instantiate this in your .qsys system you have direct access to the transceiver configuration interface. I suggest you have a look at the demo designs. For A10 you can find them here :
Hope this will solve your query.
Thank you
Kshitij Goel
Occasional ContributorHi,
I have implemented the component you mentioned, but unfortunately it does not work. I have the same error: The register Bit 0x280[2] stays at 0x1, i do not get the control over the reconfiguration interface... The memory area looks exactly like shown in my first post.
I tried it with Nios II and V there was no difference.
Why can't I get control over the reconfiguration interface? Is it possible that the so-called PreSice is not working properly?
Regards, LFrin
