Forum Discussion
LFrin
Occasional Contributor
3 years agoArria 10 cannot access Transceiver ATX PLL reconfiguration interface
Hello,
I am currently try to recalibrate the Transceiver ATX PLL on an Arria 10 FPGA (10AX027E4F29E3SG) because the reference clock is not available at FPGA configuration. I use the NIOS V and conn...
- 3 years ago
Hi,
i found the problem. It is hardware related:
I found it strange that the integrated processor, which takes care of the initial callibration, did not react. If I understand correctly, it is clocked by the 100 MHz user clock (clkusr). I checked the 100 MHz oscillator and well... it does not work. Since we don't use this oscillator for anything else, we didn't notice it earlier.
Thanks for the help, my problem is solved.
Regards, LFrin
Kshitij_Intel
Frequent Contributor
3 years agoHi,
Is your design includes an Avalon master that can access the dynamic reconfiguration registers using the Avalon® memory-mapped interface?
Can you please refer Recommendations for Dynamic Reconfiguration for TX PLLs.
Hope this will solve your query.
Thank you
Kshitij Goel