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empissas's avatar
empissas
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4 years ago

ARRIA 10 Bidir GPIO Synthesis error

Hi ,

I try to instantiate a tri-state buffer using the GPIO IP CORE . Although i assume that i had made all the connection correct the synthesis stage outcomes this error

Error(17044): Illegal connection on I/O input buffer primitive i2c_test|gpio_0|core|i_loop[0].altera_gpio_bit_i|input_buffer.ibuf. Source I/O pin i2c_test|pad_io[0] drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

The connections that i had in the top level design are the following

inout wire tri_buff;

i2c_bidir u0 (
.dout (),
.din (),
.oe (),
.pad_io ( tri_buff)
);

the tri_buff signal does not drive any other destination and i cannot understand why the above error occurs

Thanks in advance

6 Replies

  • sstrell's avatar
    sstrell
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    4 years ago

    Strange. Anything unusual about the pin you selected for this in Pin Planner?

    • empissas's avatar
      empissas
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      4 years ago

      No, nothing unusual. I assume that the pad_io signal has to be assigned an inout top level pin in order to connect to the pad . Is that right?

      • sstrell's avatar
        sstrell
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        4 years ago

        I believe so. Does it show as bidirectional in the Pin Planner All Pins list?

        Oh, since you can't synthesize, you might not even be able to do that. Hmm.

        Is the first stage of synthesis, Analysis & Elaboration, successful if you run it on its own?

  • empissas's avatar
    empissas
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    4 years ago

    I finally found why the synthesis stage had this error.

    Thanks

    • sstrell's avatar
      sstrell
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      4 years ago

      So for future reference, what was the problem?

      • empissas's avatar
        empissas
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        4 years ago

        I had also set this bidir pin as signal in the signal tap logic analyzer. This way, the synthesis stage assumed that is was driving more than one destinations.