Forum Discussion

empissas's avatar
empissas
Icon for New Contributor rankNew Contributor
4 years ago

ARRIA 10 Bidir GPIO Synthesis error

Hi , I try to instantiate a tri-state buffer using the GPIO IP CORE . Although i assume that i had made all the connection correct the synthesis stage outcomes this error Error(17044): Illeg...
empissas's avatar
empissas
Icon for New Contributor rankNew Contributor
4 years ago

I finally found why the synthesis stage had this error.

Thanks

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    So for future reference, what was the problem?

    • empissas's avatar
      empissas
      Icon for New Contributor rankNew Contributor
      4 years ago

      I had also set this bidir pin as signal in the signal tap logic analyzer. This way, the synthesis stage assumed that is was driving more than one destinations.