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xytech's avatar
xytech
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7 years ago
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Arial10 VCCT_GXB and VCCR_GXB Voltage should be 1.03V for PCIe 3.0?

Hi there, we are using 10AX057H3F34E2SG transceivers for PCIE GEN3.0 x4 lanes for Chip-to-COMe Module(PC module on board) .

As we know, PCIE 3.0 is max. 8GT/s, which is less than 10Gbps data rate max.

A10 Datasheet Table4 indicate that VCCT_GXB and VCCR_GXB should be 0.95 when data rate is less than 12.5Gbps.

However, notes(19) on the bottom of page 10 writes, "To support PCIe* Gen3, this pin must be 1.03 V (± 30 mV) or higher."

So, what the supply voltage should be for our application? 0.95V or 1.03V?

By the way, "1.03V or higher", what's on earth does the "higher" mean ? Can it exceed 1.06V??

Thanks!!!

5 Replies

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    As you mentioned PCIE 3.0 is max datarate is 8 GT/s . Per datasheet if your application is chip to chip , then both Transmitter / Receiver voltage is 0.95V Typical, but if the your application using backplane or datarate > 11.3 Gbps then the voltage is 1.03V.

    A10 datasheet Table 4 clearly indicate that VCC_GXB & VCCR_GXB should be 0.95V when datarate is < 11.3 Gbps.

    Thank you

  • xytech's avatar
    xytech
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    7 years ago

    Hi sree

    I guess the "Data rate"​ in this Intel datasheet means for EACH trasceiver lane?? Also, I think it is also ok for chi-to-chip to use 1.03V even if the data rate is lower than 11.3Gbps as long as power consumption is acceptable.

    In our application, we have PCIe3.0 x4 for Board-to-Board connection ( chip to PC-module, 8Gbps per lane, total 32Gbps). And we also have chip-to-chip connection of x10 transceiver lanes​ on one Board, with 8Gbps per lane, total 80Gbps for now, and possibly upgrade to higer data rate in future.

    I think we CAN use 0.95V for NOW. But since power consumption is not a concern, we better use 1.03V. How do you think? Thanks a lot!

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hello ,

    Answer to your first question : Yes , data rate in datasheet is for each late , here is the Intel Arria 10 transceiver phy guide: Section "Transceiver PHY Architecture Overview"

    here is the link for your reference

    https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

    Answer to your second questions , Yes , you can very well use as long as power consumption is not concern for your application. Keeping at 1.03 V also help to upgrade the data rate in future as per datasheet.

    Thank you ,

    • xytech's avatar
      xytech
      Icon for Contributor rankContributor
      7 years ago

      Thanks, Sree​. You answer really helps.