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xytech's avatar
xytech
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7 years ago
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Arial10 Power-Up Calibration Clock Question

Hi, we are using ​10AX057H3F34E2SG for PCIe GEN3.0 x4 lanes, connected to a PC module by Board to Board connects.

I read on section 7.3 of UG-01143 (Arria 10 Transceiver PHY User Guide, page582) that user need to provide a CLOCK for proper transceiver for power-up calibration, and only Power-ON Calibration are allowed for PCIe..

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Question1: Is this CLK refer to CLKUSR or dedicated XCVR REFCLK pin pairs, or both? As marked with red and blue lines in below picture. I guess both CLKUSR and XCVR clock should be provided to FPGA. But still need intel confirm.Question2: For section 7.3, what's the specific definition of "Programm" action in first sentence? Does it refer to Configuration, or Initialization, or both? Also, I'm confused that seems to be conflict between the FIRST and SECOND sentence for this paragraph. First sentence indicates that XCVR calibration start AFTER "programmed" , while second sentence indicates that calibration could continue DURING "Programming

", and may extend into user-mode.

How to understand this? I guess the seuqence should be Power on -->Configuration-->Initialization-->XCVR Calinration( user mode in parallel). Not sure......When EXACTLY the calibration begins? Is there timing diagrams on Intel docs?

Question3: To avoid the well-known “100 ms boot time requirement for PCIe”, We decide to power FPGA first, after detect the CONFIG_DONE signal be pulled high, then start PC, then the PCIe reference clock will be sent from PC to FPGA GXB banks.

However, this will be CONFLICT with UG-01143 section 3.2 , page381 note, which writes “To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration”. Do you have any insight about how could we solve this conflict?

For now, we use ASx4 config scheme, and no likely to change it for other config schemes.

Thanks very much!

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  • JonWay_altera's avatar
    JonWay_altera
    7 years ago

    Hi @xytech​

    Calibration starts during configuration.

    No timing sequence, the time for calibration to complete vary by device.

    Based on experience, faster configuration time is needed if you are designing for open-system to meet the 100ms. For closed-system, you can adjust the PERST to allow more time.

    Hope this helps.

17 Replies

  • xytech's avatar
    xytech
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    7 years ago

    @ Sree (Intel), hi Sree, if you have time, could you please kindly help on this? Thanks .

  • xytech's avatar
    xytech
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    7 years ago

    copy from other post. reocorded here.

    The total configuration timing sequence is;

    1) External power gets turned on to the "system"; motherboard or chassis, main host CPU, and PCIe bridges and devices.

    2) The power supplies for the host and the peripheral devices start ramping up. The timing for this part is completely arbitrary and depends on the system design. In the case of your FPGA-based PCIe end-point, you'll have whatever ramp time your power supplies require, and if you've specified a fast POR, they need to ramp within that time.

    3) Once the power supplies are in spec, the FPGA configures, eg., via Active Serial, Passive Serial, or Fast Passive Parallel.

    4) The BIOS or host CPU bootloader enumerates the PCIe bus. So long as (3) completes before (4), your system will work, otherwise it will not, as the PCIe device will not be enumerated.

  • JonWay_altera's avatar
    JonWay_altera
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi @xytech,

    Let me try to help out here.

    Q1: Yes, both.

    Q2: Calibration starts as soon as FPGA is powered. Cal_busy goes low to indicate calibration completion.

    Q3: The 100Mhz refclk for PCIe must be stable before FPGA is powered. See diagram of PCIe spec, FPGA should configuration within point (3). Link training is somewhere within (4).

    Hope this helps.

    • xytech's avatar
      xytech
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      7 years ago

      Hi JwChin, thank you very much for patient reply.

      For Q2, As you mentioned “Calibration starts as soon as FPGA is powered”. Is it start AFTER or parallel with Configuration Starting Moment? This confusion came from between First and Second sentences on page582 section7.3 of ug-01143 ( as pic in my original post). And Is there some Intel document describes the timing sequence of related signals ?

      According to you information, it seems that we have no choice but to change our config scheme from ASx4 to FPP for faster configuration time. Or we might use Partial Reconfiguration or Configuration Data Compression, but it will consume more work for our FPGA staffs.

      Thanks again, and look forwar to your discussion.

  • JonWay_altera's avatar
    JonWay_altera
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    7 years ago

    Hi @xytech,

    There are two main types of calibration.

    • Power-up calibration—Initiates automatically at device power-up and runs during device configuration.

    • User calibration—If you perform dynamic reconfiguration or change the reference clock frequency of the I/O PLL, you must perform user recalibration. You must enable the required calibration sequence.

    With that, answer to "Is it start AFTER or parallel with Configuration Starting Moment?" should be parallel with the configuration process.

    There is no timing sequence for the calibration process as the time required after device power-up to complete the calibration process can vary by device. That's why you will need the cal_busy signal to know when it completes.

    Just my 2 cents, as to ASx4 to FPP, I think it depends the PCIe is used for open-system (need to meet 100ms requirement) or closed-system (up to you to decide). If it is a closed-system, I dont see why you need to change to FPP, you can delay the #PERST to allow more time.

    I hope this helps.