Forum Discussion
ContributorArial10 Power-Up Calibration Clock Question
Hi @xytech
Calibration starts during configuration.
No timing sequence, the time for calibration to complete vary by device.
Based on experience, faster configuration time is needed if you are designing for open-system to meet the 100ms. For closed-system, you can adjust the PERST to allow more time.
Hope this helps.
Frequent ContributorHi @xytech,
Let me try to help out here.
Q1: Yes, both.
Q2: Calibration starts as soon as FPGA is powered. Cal_busy goes low to indicate calibration completion.
Q3: The 100Mhz refclk for PCIe must be stable before FPGA is powered. See diagram of PCIe spec, FPGA should configuration within point (3). Link training is somewhere within (4).
Hope this helps.
xytechHi JwChin, thank you very much for patient reply.
For Q2, As you mentioned “Calibration starts as soon as FPGA is powered”. Is it start AFTER or parallel with Configuration Starting Moment? This confusion came from between First and Second sentences on page582 section7.3 of ug-01143 ( as pic in my original post). And Is there some Intel document describes the timing sequence of related signals ?
According to you information, it seems that we have no choice but to change our config scheme from ASx4 to FPP for faster configuration time. Or we might use Partial Reconfiguration or Configuration Data Compression, but it will consume more work for our FPGA staffs.
Thanks again, and look forwar to your discussion.
