Are these Verilog statements synthesized as parallel HW?

Hi,

I have 32 different 32 bit- registers where I need to add the numbers of ones in each of them in parallel, to simplify :

begin

A = R1[0] + R1[1] + R1[2] ....... + R1[31];

B = R2[0] + R2[1] + R2[2] ....... + R2[31];

C = R3[0] + R3[1] + R3[2] ....... + R3[31];

D = R4[0] + R4[1] + R4[2] ....... + R4[31];

end

Is the following code synthesized as parallel adders in HW or not? If not, how can I do that, fork/join statements are not supported in Quartus II

Thanks