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Altera_Forum
Honored Contributor
Honored ContributorAre Pll outputs in phase between different PLL when using the same reference clock
In the following scenario, If I have PLL A and PLL B driven from the same input reference clock (50MHz). Each PLL creates a 200MHz clock with no phase shift. The PLL is set in 'no compensati...
Altera_ForumHonored Contributor
Honored ContributorMy answer to your original question 4 is clearly wrong. You can clearly specify the phase between input and output clocks in the PLL, thus removing any timing dependency from the reset.
