Are Pll outputs in phase between different PLL when using the same reference clock

There's actually advantages to using clock-crossing logic regardless of whether the different clock domains are an integer multiples or not;

1. It allows Quartus to consider them separate entities, so they can be placed-and-routed in isolation, eg., you can use LogicLock regions to help "encourage" the fit.

2. It allows you to change the clock frequencies of the different domains as your design evolves.

This scheme is useful in DSP processing pipelines, where high-speed data is filtered and transferred to the next processing blocks, where those processing blocks have different levels of parallelism.

It can sometimes make your head spin trying to think about it ... but it does make the P&R easier, and provides fine control of the timing.

Clock-domain crossing logic is not particular "expensive" in terms of logic resources. For example, 10 ALMs can be configured into dual-ported dual-clock 640-bit memory (32 x 20-bits or 64 x 10-bits). That is not much of a price to pay, when you gain separation of clock domains.

Cheers,

Dave