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Altera_Forum
Honored Contributor
Honored ContributorAre Pll outputs in phase between different PLL when using the same reference clock
In the following scenario, If I have PLL A and PLL B driven from the same input reference clock (50MHz). Each PLL creates a 200MHz clock with no phase shift. The PLL is set in 'no compensati...
Altera_ForumHonored Contributor
Honored ContributorI don't understand the reasoning behind answer 4. When the PLL locks after releasing the reset, the phase relation between reference and output clocks is etablished. Presuming an output frequency that's an integer multiple of reference, the phase won't depend on the reset time and is kept as long as the PLL stays locked.
As a result, we can expect the discussed timing skew between same frequency outputs of different PLLs, but no addon due to reset timing.
