Are Pll outputs in phase between different PLL when using the same reference clock

I will offer my thoughts on the subject but suggest you consider them in conjunction with any other responses you receive.

1) They are NOT likely to be in phase. Whether you feed both PLLs with the same clock source driven into the same pin OR feed the both PLLs with the same clock source routed to each PLLs respective clock input pin, the routing delays are going to be different, both internal and external. So, the PLL outputs are going to be out of phase as well.

2) My answer to question 1 aside, assume they are in phase. Theoretically, you now have identical clocks whose edges line up. Setup and hold times alone will ensure the transfer between domains works. However, now considering my first answer. With an indeterminate phase shift you clearly can't reliably transfer directly between domains.

3) Timequest should be able to pick up the post routed relationship between the two clock domains.

4) Yes. Releasing the resets as you suggest, or even simultaneously to both PLLs (remember routing delays), will result in further phase difference.

This feels like a slightly academic scenario. I'd suggest you shouldn't consider anything like this in the interests of reliability of a design. Given the relatively small amount of FPGA resource you need to take a signal from one domain to the other, you should just be putting that extra logic in.

Regards,

Alex