New ContributorThis file would have information under [Define Package Model] in an IBIS file and be specific for each FPGA package. It correlates to the netlengths available on the website used for DDR/high speed length matching and analysis. Thanks!
Frequent ContributorHi Sir,
Here is the IBIS package available for all FPGA device, including Arria 10.
https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html
IBIS model is depend on which IO standard and termination setting that you set in the Quartus design.
New ContributorFrequent ContributorHi Carolyn,
As I know, that is the only IBIS model that available. It allow you to run the IBIS simulation based on specific IO. If you want o include the package delay, you can get the pin net length following the instruction as stated in this link: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07122010_270.html
Hope this helps
Frequent ContributorI’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
