Architecture timing issue

iozana,

It's hard to know beforehand exactly how much combinational and routing delay there is.

You need to set a 10 MHz clock constrain , then synthesize the design (or the VHDL module) and run the static timing analysis (TimeQuest) to see if the constrains can be met.

Check the TimeQuest cookbook for details.

But experience tells us that in this particular case, no. A 24 bit divider is too big and has too much delay to run at 10 MHz in a single cycle. Thus, you need to pipeline the design or make it multi-cycle.

However, I'm not sure you need to use an IP block.

If you pass the division's output through several levels of registers, Quartus is smart enough to distribute the combinatory logic through the several register levels.