Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi Pete,
--- Quote Start --- Sounds like the first master is not giving up the bus. IE it's trying to do LARGE reads, so it gets them once it's request is granted. --- Quote End --- Yes, using Signal-Tap I can see, that the first master constantly assigns request signal. My problem is, that the master is a Generic Tri-State Controller, so I have no access to request/grant. --- Quote Start --- But can be corrected with a custom module placed that converted the large transactions into smaller one if required. --- Quote End --- Accessing the GTC via MM-Master I de-assert the read signal as soon as waitrequest is low and only assert it after readdatavalid goes high. So each word is read separately with 2cc where read is low, but this doesn't make the GTC de-assert the request signal! Of course I can make larger gaps between successive reads or write my own custom TC, but I was looking for a smarter way to get a fair arbitration :) Simon