Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAppropriate ADC for educational project?
Hello folks!
I'm a student of 'Network Systems and Data Communications' department in Greece and am doing my final project/dissertation right now in Leiria, Portugal at Electrical Engineering department. Because the subject is kind of complex, I'm going to introduce to you only the part on which I'd like to set my specific question. I want to implement a small device/circuit which will be inputted some analog voice commands from a normal electret mic. Till now I'm not clear about what pre-amp/op-amp I should use, but I believe I'll figure this out. The implemented circuit will be interfaced onto a Pluto-II (Cyclone-I) FPGA board, probably SPI/i2c will fit the best. I've read a lot about ADC's appropriate for voice/audio systems, and I suggest that an Σ-Δ (sigma-delta) ADC will be good for me, in combination of a simple low-pass anti-aliasing filter consisting of a resistor and a capacitor in parallel before the ADC. Actually, regarding the Σ-Δ ADC I still have no clear image if it is a linear or logarithmic ADC, cause as far as I know, it should be a logarithmic one for audio sampling, isn't it? Considering a specific topic of your forum and obvious knowledge you people got, I thought that maybe you could suggest to me any appropriate market ADC for my purpose. Thank you! Sincerely, David32 Replies
Altera_ForumThe ADS1202 application notes (for motor control) have VHDL code on how to interface with it.
- Altera_Forum
Thank you very much!! It was very helpful. We have a very good waveform of 300-500 mV Peak-to-peak.... i think it will work properly.
The next wondering is about sigma-delta adc and the vhdl code we have to implement on the FPGA. Is there any book, referense which will help us at any level? thank you again!!!! - Altera_Forum--- Quote Start --- Can anyone explain me because i am a little confused, which voltage should i input!!!? --- Quote End --- The first specification is from absolute maximum ratings, this voltage can be applied without damage. For correct ADC operation, both common mode and differential input voltage specification have to be kept. +/-250 mV differential input voltage is the nominal range.
- Altera_Forum
Amilcar,
could you please send me your email, because I'm not able to send any PM yet. I got some further questions regarding the adc you recommended me! Thanks in advance! - Altera_Forum--- Quote Start --- I just interestingly noticed that the input range of ads1202 is -250mV to 250mV, is that okay for voice processing? So that would be nice because I'd get rid of some noise amplifying the mic's signal less than expected. --- Quote End --- About the Input Voltage i haven't got that. How much voltage it should be inputted? I am not so experienced but the Datasheet says that the Analog Input Voltage Range ......................... GND – 0.4V to VDD + 0.3V Vdd=+5v Gnd= 0v And at the specs it has this Vin. +In = –250mV to 250mV Can anyone explain me because i am a little confused, which voltage should i input!!!? FvM thank you for your help but some of your answers are hard to understand because your knowledge is by farrr better that ours!!!! Regards Giannis
- Altera_Forum--- Quote Start --- Also, I didn't exactly understand the role of decimation of the delta-sigma?! --- Quote End --- ADS1202 is special in so far as it's only a SD modulator rather than a complete SD ADC. The latter would include the decimation function and output parallel data at the specified rate. The ADS1202 sends a bit bit stream at the SD oversampling frequency and needs external decimation to work as a full-featured ADC. The main reason, why the ADS1202 has been designed this way is because it's intended for operation through a isolated serial interface. But it's also a versatile building block for a FPGA analog front end. You should refer to the basic SD converter theory, if you are interested to learn more about the role of decimation in SD operation, particularly noise shaping. But I think, the ADS1202 applications give some insights. A sinc^x filter (CIC decimator is just another word for it) hasn't a steep characteristic. If you decimate voice data to a moderate sampling frequency (e.g. 8 to 16 kHz) with this filter, high frequent signal components would be attenuated considerably, you may want to add either a correction filter or use a decimator with different characteristic in the final step of a multi stage decimator design.
- Altera_Forum
I just interestingly noticed that the input range of ads1202 is -250mV to 250mV, is that okay for voice processing? So that would be nice because I'd get rid of some noise amplifying the mic's signal less than expected.
- Altera_Forum
Dear amilcar,
I'd firstly like to introduce myself: My name's David and I'm actually Austrian, having grown up in Greece. It obviously seems like I got to make some experience with the filtering part, as I've not dealt enough with it. I'd appreciate if you could send me the code for the sinc^3 filter, so I can start from somewhere. Also, I didn't exactly understand the role of decimation of the delta-sigma?! Anyway I'll check out that stuff! We can also speak German if you want, but I'd prefer English because of terminology! :-) Thank you very much for your interest! Sincerely, David - Altera_Forum
Yes, you can send 20MHz clk to the ADC, but that ADC will send you a clk signal back, and you need to use that one to clock the data in.
You can and should build the low pass filter together with the decimation of the delta-sigma. And the best way to achieve that on an FPGA is to implement the sinc3 filter described in the application notes of that chip. I can send you the code if you want. I have no experience with the NE5532. - Altera_Forum
Fvm, thank you for your reply!
I'm sorry of not mentioning the bit-resolution I've thought about, but I was actually also considering of using a 12-bit resolution ADC. Thank you anyway! amilcar, what nice coincidence! I checked out the ADC you recommended, and it looks good to me! Just a few things to clear out... I saw that I can use an external CLK in mode 3 of ads1202 for application requirements, so that I can synchronize the data output with the fpga. That's important to me because I need to transmit data from the fpga via 10Base-T Ethernet which needs 20 MHz of minimum bandwidth. Is that right? Also, due to oversampling of the device and the integrated DSP I won't need any further low-pass filter, is that so? Finally, I thought of using NE5532 pre-amp as an op-amp. Will this work together properly? Thank you all for your time!
