Appropriate ADC for educational project?

Yes, you can send 20MHz clk to the ADC, but that ADC will send you a clk signal back, and you need to use that one to clock the data in.

You can and should build the low pass filter together with the decimation of the delta-sigma. And the best way to achieve that on an FPGA is to implement the sinc3 filter described in the application notes of that chip.

I can send you the code if you want.

I have no experience with the NE5532.