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Altera_Forum
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19 years ago

Apparent Reset Glitch on Synchronous Reset

While running SW tests, at random times it looks like all my internal registers are getting cleared to their reset values. This is true for both registers and SOPC modules. Depending on the SW I ru...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

I finally captured some new information.

I added two 15bit Altera MegaCore lpm_counters to the top level BDF and added the output of both to SignalTap.

- CounterR has clk and an asynch reset

- CounterNoR has clk only.

After power on I see the CounterR count lag by 17h which makes sense since it will start later due to reset signal.

I captured the error, and I see CounterR being cleared to 0 BUT CounterNoR keeps counting without errors. On the next clock CounterR is 1 so it is not held cleared.

Here are the 5 clock values surrounding the error:

CounterR: 30B5 30B6 0000 0001 0002

CounterNoR: 30CC 30CD 30CE 30CF 30D0

I have the FF that generates the asynch reset signal as well as the asynch reset signal being captured in SignalTap and I don't see them go active - same behavior as before.

After typing all this I captured the counters and they have the same 0x30CE offset.

This seems to imply that it is the reset signal causing problems.

I'll try to get the asynch reset on a pin and hook up a scope and see what I see. We're a bit pin constrained so this may take a bit to find a pin that doesn't conflict with other logic.

Thanks,

Stefan