Honored Contributor
Honored ContributorApparently I was a bit sleepy when I wrote the original email cause I agree the title is confusing (although I didn't think so at the time :-) ).
Yes, all the Reset registers and the reset of the design use the same clock. The reset registers only use D, CLK, and Q. The signals that I captured under SignalTap run the gambut: Altera's PIO output, external bus address latch, data register in SOPC Module, control signals from state machine. Design has combination of verilog for SOPC modules and AHDL for state machine block plus some schematics. I added a counter and some other logic that just uses the clock and an asynch reset to see if these are cleared as well. Of course, with this new logic I can't reproduce the problem. I'm still tinkering to get one that fails again. We're also looking into noise on the voltage pins. This would have to clear the registers in the FPGA (appear like reset) but NOT touch the FPGA image since the FPGA is still programmed. Is there anything else like this that could cause problems that we should check in the PCB? Thanks for all your help. Stefan
