Altera_ForumHonored Contributor18 years agoApparent Reset Glitch on Synchronous Reset While running SW tests, at random times it looks like all my internal registers are getting cleared to their reset values. This is true for both registers and SOPC modules. Depending on the SW I ru...Show More
Recent DiscussionsAgilex 3 PLL in Source Synchronous mode ?writing a word to cfm1 using on chip flash ip on max10MAX10 FPGA IOs not entering Tri-state (Hi-Z)To INTEL - Request for Compliance Data from your customerPower-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices