Apparent Reset Glitch on Synchronous Reset

Hi Stefan ,

In your design , is there any reset case like this one ?

------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity glitch is

generic

(

RESET_VAL : natural := 170;

WIDTH : natural := 8

);

port

(

areset : in std_logic;

clk : in std_logic;

ena : in std_logic;

Q : out std_logic_vector(WIDTH-1 downto 0)

);

end entity glitch;

architecture behavioral of glitch is

signal cnt : integer range 0 to RESET_VAL-1 := 0;

begin

process (areset, clk, cnt)

begin

if areset = '1' then

cnt <= 0;

elsif cnt = RESET_VAL-1 then

cnt <= 0;

elsif clk = '1' and clk 'event then

if ena = '1' then

cnt <= cnt + 1;

end if;

end if;

end process;

Q <= conv_std_logic_vector(cnt, WIDTH);

end behavioral;

------------------------------------------------------------------

I have tried this before , I evaluated it in a MAX II Device EPM570T100C5

Everything works fine in TIMING simulation in Quartus II

However when I downloaded the program to the CPLD

(actually it is not only a counter design , a total of 570 LE)

Then I checked the signal waveform on the scope

I have found that the coutner part is reset to zero in an average of 19 rounds

but it failed to reset (not returning to zero) at 20th round in an average

The solution is :

process (areset, clk, cnt)

begin

if areset = '1' then

cnt <= 0;

elsif clk = '1' and clk 'event then

if ena = '1' then

if cnt = RESET_VAL-1 then

cnt <= 0;

else

cnt <= cnt + 1;

end if;

end if;

end if;

end process;

I am not sure if this is your case , Hope it helps

Cheuk