Apparent Reset Glitch on Synchronous Reset

I'm doing a full recompile. I'm using the web version in my office.

I think I was not quite clear on the internal reset signal. The internal reset signal is used asynchronously throughout the design, both in top level blocks and passed to SOPC Builder.

This internal reset signal is being generated from the output of a DFF whose input is the OR of 2 other DFF outputs.

Using SignalTap I captured the failure event. I was watching 12 asynchronously reset registers and the 3 DFF's involved in the reset. I do not see the 3 reset DFF's change value. I do see all 12 of the other design registers that were high get cleared on the same clock edge in SignalTap.

The same clock is used throughout the design.

I'll implement the toggle suggestion you had and try that tomorrow.

Thanks,

Stefan