Apparent Reset Glitch on Synchronous Reset

I think some more debugging is going to need to be done. Let's just say a glitch is occuring, and let's make it long, like 100ps. If the fanout of the net is to many registers, the delay to all of its destinations will vary by much more than 100ps. Since it's a synchronous reset, then this 100ps pulse would have to hit every register at exactly the same time as the clock edge is hitting them, which I would say is close to impossible. My guess is that it's not just a glitch, but a full logic change for a cycle. Are you able to capture it with SignalTap?

If you can't outright capture it in signaltap, anohter idea is to have the signal clock a toggle register or a 2-bit counter. Then capture the toggle register or counter by SignalTap. If the glitch is long enough to set all your registers, it should cause the flop or counter to switch states, and you should be able to capture that in SignalTap. If you can't capture that, then I doubt that is the signal that is truly causing the problem.

And when you change SignalTap and the results change, are you doing a full recompile, so your whole design is re-fit, or are you doing an incremental compile, so only the SignalTap nets are changing?