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Altera_Forum's avatar
Altera_Forum
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17 years ago

AP configuration problem

I am a FPGA beginner , I designed a board with cyclone III and Intel P30 (128P30B)flash (just like the cylone III starter eval kit), my board is designed for supporting JTAG and AP configuration. when I cofigure the FPGA in AP mode, Quartus II 7.1 programer erased the flash(0x000000 ~ 0xFE0000 ) and programmed the flash (0x20000 ~ 0x380000) and notice me 'successfully'. the problem is that the FPGA can not be configured when I power it on or nConfig the FPGA again .

why it occurs ? is the programmer erased the parameter block of FLASH ?

looking forward to your reply, thanks.

PS: I found the nStatus of FPGA is sometimes low.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You need to copy your FPGA configuration file (*.sof or *pof) into the intel flash. After power up your board, the FPGA internal circuitry should automatically load the configuration file (stored in flash) to the FPGA.

    1. Check your FPGA configuration pins (MSEL0 to 3) are set correctly to get this behavior (refer to the datasheet). These pins should be configured to use AP configuration, check also nStatus, config_n and ce_n pins... (refer to the reference schematic from the eval board)

    2. Before use the programmer to load the configuration file you probably need to convert your *.sof file into a *jic file (which mean "indirect JTAG") in order to load it into the flash and not directly into the FPGA (I need to do that with my serial flash data).

    I hope it will help you,

    Enjoy,

    -Pierre
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    the Quartus programmer is indicating that it has programmed the FLASH correctly NOT that the FPGA is configured correctly.

    You mentioned that nStatus is "sometimes" low

    To quote Altera "When a configuration error occurs, the FPGA drives nSTATUS low, which resets itself internally. The FPGA will release its nSTATUS pin after a reset time-out period."

    Have you proved that your PCB design is correct? i.e. Have you managed to get any image working in your FPGA?

    I have come across several designs whereby the simplest of things prevent the FPGA configuring correctly. For example the MSEL pins as Pierre mentioned. Also check that all Power pins are connected correctly. I have seen a Stratix II device fail to configure because power to a PLL used in the design was missing. I would advise a total check of all pins in your PCB schematic....Boring but always worth it in the long run!

    Rgds

    Vern