AP configuration problem

Hi,

the Quartus programmer is indicating that it has programmed the FLASH correctly NOT that the FPGA is configured correctly.

You mentioned that nStatus is "sometimes" low

To quote Altera "When a configuration error occurs, the FPGA drives nSTATUS low, which resets itself internally. The FPGA will release its nSTATUS pin after a reset time-out period."

Have you proved that your PCB design is correct? i.e. Have you managed to get any image working in your FPGA?

I have come across several designs whereby the simplest of things prevent the FPGA configuring correctly. For example the MSEL pins as Pierre mentioned. Also check that all Power pins are connected correctly. I have seen a Stratix II device fail to configure because power to a PLL used in the design was missing. I would advise a total check of all pins in your PCB schematic....Boring but always worth it in the long run!

Rgds

Vern