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Altera_Forum's avatar
Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

And the magic answer is:

Run a bunch of random seeds (Takes days on server farm as a single run takes 24 hours).

Change fitter and router effort to 4.0 and 3.0 respectively

Change synthesis from Speed to Balanced (Dropped size down by a few percent)

Remove all design partitions (Design partitions were taking us farther and farther away from final solution). Once they were removed, size of design dropped from 95 to 90 percent full.