Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Just some brainstorming (I mostly use Cyclone, so maybe something does not really apply for Stratix):

- Try to reduce the number of used logic (maybe, with 90% it would fit like a charm), either by changing the RTL-code and / or by changing compiler-options (e.g. maximum register-packing, optimze for area instead of optimze for speed)

- You mentioned 200 clocks. The clocks with failing paths, are they using global clocks or non-global routing-resources? If they use non-global, try to reduce the number of clock-domains so that only global resources are needed (this would also free routing-resources for normal routing).

To get an impression: What frequencies do you want to achieve, what is your "typical" slack in the moment?

Thomas