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Altera_Forum's avatar
Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Hi,

sounds really difficult. Do have still partitions in your design ? 95% uitilization means logic cells, memory ... ??? Can you post your design summary here ?

Kind regards

GPK

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100% of memory and 95% of logic.

I have another question about how tool allocates memory. The fitter seems to use 100% of memory and then starts chewing up internal logic. Anyone know of any documentation that describes this?