Anyone ported AN532 PCIe to Arria2GX dev kit?

I am also trying to port AN532 to the Arria II GX Dev Board but having no luck. What I did find in the PCI Express Compiler User Guide in the SOPC Builder Design Flow Chapter 2 is a paragraph saying " For Stratix IV GX and Arria II GX designs, you must instantiate the ALT_RECONFIG megafunction and connect it to three pins from your SOPC Builder system that are required to dynamically reconfigure the transceiver.....

reconfig_Clk_<PCIe_Compiler_Instance_name>

reconfig_fromgxb_<PCIe_Compiler_Instance_name>

reconfig_togxb_<PCIe_Compiler_Instance_name>"

But I still couldn't get the LINUX system to recognise the board. Whereas loading the factory default works OK with LINUX showing the correct Device ID etc.

Is your FPGA design working but you are only having problems with the GUI OR you are having problems with both?

Hi all,

i'm trying to port AN532 to the Arria II GX devkit, too. I encounterd the very same problems that are mentioned above. I did not yet try to connect the reconfig block. Can you tell me if it helps?

I sucsessfully created a project from the megawizard example chaining dma and got it working with Quartus 9.1 . Even the linuxdriver altpciechdma works once after a reboot. I think this is a x8-pcie-endpoint.

I need a x1-pcie-endpoint, so i connected the signals PCIE_RX_{P,N}0 and PCIE_TX_{P,N}0 to the pins mentioned in the "Arria II GX FPGA Development Board" on the sopcsystem that is like that one in AN532. It did not work with my own sopcsystem and i thought that could be the problem.

Has someone created a working sopcsystem for the Arria II GX Development Board?

Regards,

Frederik

Hi Frederik,

I did managed to get AN532 ported to the Arria II GX dev board but endure a lot of pain on the way.

You MUST connect the reconfig block in, also don't follow Altera example of using the ref_clk divided by 2 as the reconfig_clk. The ref_clk should only go to the PCIe IP itself and nothing else. The reconfig_clk range of 37.5MHz to 50MHz must be adhere to.

My design path is via the SOPC Builder and not with the megawizard method.

This might help you but it is only x4 lane :

set_location_assignment PIN_AE29 -to pcie_refclk

set_location_assignment PIN_N1 -to pcie_reset_n

set_location_assignment PIN_AN33 -to rx0

set_location_assignment PIN_AL33 -to rx1

set_location_assignment PIN_AJ33 -to rx2

set_location_assignment PIN_AG33 -to rx3

set_location_assignment PIN_AM31 -to tx0

set_location_assignment PIN_AK31 -to tx1

set_location_assignment PIN_AH31 -to tx2

set_location_assignment PIN_AF31 -to tx3

set_location_assignment PIN_AJ19 -to clk_in

set_location_assignment PIN_N10 -to reset_n

Regards,

Peter

Hi PeterCH,

thanks for the rapid answer.

I don't see a reset_n in my design.

And I have some pins you didn't mention: gxb_powerdown_pcie_compiler_0 and pll_powerdown_pcie_compiler_0 (inputs) and rate_ext_pcie_compiler_0 and clock outputs (output). I'm using Quartus 10.0 . Don't you see this signals? Should I try Quartus 9.1 rather than the new version?

My clock was connected to F18(p) and F17(n). I will test your locations.

Regards,

Frederik

Frederik,

All inputs at the top level can be left unconnected. In VHDL, just declare a signal called gxb_powerdown_pcie_compiler_0_sig and connect that to the vhdl instantiation. DO the same for the other inputs.

You can use the 125Mhz clock output from the PCIe IP as your application input clock instead of the local_clock.

The MOST IMPORTANT signals is actually the test_in, see below:

test_in(39 downto 16) <= (others => '0');

-- selects the layer to output onto the test_out bus

test_in(15 downto 13) <= "000"; -- selects the Lane

test_in(12) <= '0'; -- selects VC

test_in(11 downto 8) <= "0010"; -- 0000 = Transaction Layer, 0010 = PHY-MAC outputs

test_in(7) <= '0'; -- Disable low power state negotiation

test_in(6 downto 5) <= "00"; -- b5 = completely disables compliance mode; never enter compliance mode

-- b6 = forces compliance mode.

test_in(4) <= '0'; -- Remote Boot mode

test_in(3) <= '1'; -- FPGA mode. Set to '1' for an FPGA implementation in order to appear compliant to other PCI Express components.

test_in(2) <= '0'; -- Descramble mode

test_in(1) <= '0'; -- Loopback Master

test_in(0) <= '0'; -- Simulation mode

Regards,

Peter

Hi PeterCH,

what I tried to do is to leave out the test-signal and to connect the sopc-system directly to the FPGA-pins. Is that wrong? Did you write a wrapper around the system?

I realized that in AN532 a wrapper is needed to tie the reconfig-inputs to fixed values. I don't have a reconfig-block in my system. I am trying Quartus 9.1.

I just want to create a very small system to do some evaluation on it. That consumes a lot of time.

Thanks in advance,

Frederik

Frederik,

Quartus 10 is fine. I have been using that for sometime.

I did write a wrapper in vhdl with the sopc component as an instantiation.

You can add the reconfig module in the wrapper and also the reconfig_clk generator.

The original AN532 did have a verilog wrapper which you can download from the dev kit area, and that will give you some idea.

Regards,

Peter

Hello Peterch,

ok, that is what i needed to know.

I'm writing the wrapper taking the <sopc>_inst.vhd . I will tie every unused signal to '0', but test_in in that way you showed obove. Is that ok?

Maybe you could post your working wrapper. I think others would appreciate it.

Regards,

Frederik

Frederik,

Here is my wrapper. Mine is a x4 lanes PCIe design. I have also re-defined the LCD connector so that I can connect some Logic Analyser probes to check out a few things. You could of course use the SignalTap II to probe your design.

regards,

Peter

Hi Peter,

tahnk you for the answer.

My design still doesn't work. I read that i need the reconfig block but it isn't generated and i can't choose PCI reconfig in the Megawizard from the SOPC builder.

Where did you get yours? Maybe that's a problem with Quartus 10.0? It's "N/A" - not available. If i start the Megawizard manually the option is available.

The pcie reference clock from the motherboard is 100 MHz. Do you confirm that a division by 3 works? I ask, because it's less that 37MHz that you mentioned in your wrapper.

Regards,

Frederik