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Altera_Forum's avatar
Altera_Forum
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16 years ago

Anyone can run DDR2 stably with Stratix IV?

Anyone can run DDR2 stably with Stratix IV and Quartus 9.1 Sp2 or above?

I've tried about 8 board(the same PCB layout) which has 1 Stratix IV 530 ES device and 7 Stratix IV 530 FPGA. The board with ES chip can run stably, other boards run unstably.

0) All calibrations are OK. can read and write data. But it's unstable.

1) Reset 10 times, PNF will fail in a few seconds for about 2 or 3 times. Other resets can run about ten or twenty minutes.

2) I only use the generated "high performance controller(it uses Altmemphy, not UniPHY)" and the driver and the example top. No other design.

3) It runs at about 166MHz at PHY side. 333MHz or 266MHz have the same result. So I don't think it's the problem of PCB layout.

4) I've used the "debug-toolkit.zip" to debug. It's weird that all 4 DQS group(32-bit) looks good enough. But the "interface level" result is BAD. The center sample point is near to the left invalid step. I almost thought that this can directly cause the instable DDR2 operation. A picture has been attached.

Thanks a lot for all your opinions!!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    No one has run DDR2 in Stratix IV stably?

    I only run at 166MHz(full rate) and 266MHz(half rate) and all SDC have been meet. But 266MHz design can run at about 240MHz.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I've had issues, usually due to lack of board trace models in Quartus or getting the Addr/Cmd phase wrong. Once these are accurate I generally dont have any issues.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    What's the PHY speed you were running at? and the FPGA device / speed grade?

    Mine is -4 speed. I still have the problem after ajusting "Addr/Cmd clock setting" to 240 (looks the best for the board,please ignore the picture I attached. It was the problem of "Addr/Cmd clock setting") and "Addr/cmd to CK skew" from 0.3ns to -0.3ns.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi All,

    thanks! The problem has been resolved. The problem is the DLL and the board power supply.

    DLL dqs delay output varies too much according the ripple from power supplier(about 100-150mv).