Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi,
What's the PHY speed you were running at? and the FPGA device / speed grade? Mine is -4 speed. I still have the problem after ajusting "Addr/Cmd clock setting" to 240 (looks the best for the board,please ignore the picture I attached. It was the problem of "Addr/Cmd clock setting") and "Addr/cmd to CK skew" from 0.3ns to -0.3ns.