Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Any ideas why this code isn't working

Backgroung, working with Terasic DE1 kit Trying to grab serial data from Copernicus Chip, interface http://www.sparkfun.com/datasheets/G...cus_Manual.pdf by default chip should give us $GPGGA onc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

By using Verilog part select expressions, most of your text collapses to a few lines, e.g.: 

gpstream<=bitstreamin;

Generally, it can't be seen, if your code uses an edge sensitive always block as required. So you may want to throw away the bitwise assignment garbage and show the overall structure, too.