any document about chip planner?

Just to clarify, note that there are "sub-models" beyond this. For example, the exact same path will have a slightly different delay in the same timing model depending on if you're doing a setup analysis or hold analysis. This accounts for On-Die Variation(amongst other things). A graphical tool can't really show all this. TimeQuest is the place to get the numbers.

Two things I use that aren't always obvious:

1) Go to TimeQuest and report a number of failing paths. Highligt a column of them all(doesn't matter which one) and right-click Locate Path -> Chip Planner. In essence you use TimeQuest's report_timing to craft the paths you want to look at and view them in the Chip Planner.

2) If you're doing Incremental Compilation, the Partition Planner task view(top-right pull-down) shows a different color for each one. But you don't have to do IC to see this. First launch the Tools -> Design Partition Planner. Grab a large hierarchy, right-click and Extract from Parent. Note that this does absolutely nothing to the design, it just helps you visualize it in this tool. Once you've done that to a few hierarchies, launch Chip Planner(both windows open) and go to the Partition Planner view. All the hierarchies you extracted should now be color coded. It's not overly useful, but helps me visualize where the fitter puts things, which is interesting to begin with, and comes in handy if floorplanning or anything like that.