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Honored Contributor
Honored Contributoranother question
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Ttrigger2 is port(t,clk:in std_logic; q:buffer std_logic); end Ttrigger2; architecture b of Ttrigger2...
Altera_ForumHonored Contributor
Honored ContributorMove the line signal qq:std_logic; between architecture and begin.
In addition, you should use a if rising_edge(clk) condition, otherwise that code won't work.
