AND vs XOR gate

In an ASIC if I remember correctly the XOR gate will be larger transistor wise than an AND gate. Like Kaz said, ASICs don't use lookup tables to implement logic since they are not designed to be reprogrammed. When you program an FPGA one of the things you are doing is programming the lookup tables to implement your combinatorial logic. In an ASIC this logic are just static transistors which keeps the size and power down.