AND vs XOR gate

Hi,

ASIC design is different world from ours(the fpga). Though it is based on RTL usually. You will need to refer to their literature but it certainly does not use lut. Instead it is based on standard cells. Each vendor provides a library of these cells.

The cells are designed at transistor level to directly implement some logical functions e.g. and,or,nand etc as well as registers/flips.

The vendors are free to choose and design their lowest level functions in whatever way. The library or the user can combine these cells to produce higher level functions.

Si, I believe, the answer depends on the cells you choose.