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Altera_Forum
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15 years ago

And operation in VHDL

Hi, How can i use AND logic operation between 2 std_logic_vector?
Altera_Forum's avatar
Altera_Forum
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15 years ago

did you include the std_logic_1164 package?

There are and functions for std_logic/std_ulogic and std_logic_vector/std_ulogic_vector. Not just boolean and bit.