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Altera_Forum's avatar
Altera_Forum
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15 years ago

And operation in VHDL

Hi, How can i use AND logic operation between 2 std_logic_vector?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes but what about a AND between std_logic_vector??

Moreover ,AND operation is for boolean and the modelsim gives an error for std_logic.

THX