Forum Discussion
Altera_Forum
Honored Contributor
9 years agoRead through the "altpll_reconfig user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altpll_reconfig.pdf)". This IP allows you to reconfigure the PLL from the FPGA fabric, whilst it's operating.
The ALT_PLL IP has a static configuration, determined when the FPGA is configured. See the "alt_pll user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altpll.pdf)" for comparison. When you might use each depends on your requirements. Cheers, Alex