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MartinMaa's avatar
MartinMaa
Icon for Occasional Contributor rankOccasional Contributor
7 days ago

ALTPLL - BANDWIDTH OPTION ?

Here is a professional and technically accurate English translation:

Hi,

I would like to ask about the meaning of the following setting in ALTPLL:

Bandwidth - Preset
Options: Auto, Preset (Low, L, H), Custom

What is the purpose of this setting?

I am using the FPGA device 10M02SCM153C8G and implementing an SCFIFO. Due to the signal logic requirements, I need to generate a stable 180-degree phase-shifted version of the signal and feed it into the SCFIFO, as well as to the FX2 IFCLK connected after the SCFIFO.

Currently, I am encountering a very rare issue: image tearing (or frame splitting).
My system architecture is: sensor → FPGA (FIFO) → FX2 → PC. Although this issue occurs very infrequently, I would still like to explore possible improvements.

Previously, the FPGA setting was configured as Auto, and under this condition, the image tearing issue occurred more frequently. After changing the setting to Low, the system became significantly more stable.

I am now considering whether to try the Medium setting, but before making further changes, I would like to understand what this bandwidth setting actually controls.

Would you like me to refine this into a more formal email style (for vendor support like Intel/Altera), or keep it as a technical discussion tone?

 

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1 Reply

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    16 hours ago

    Thank you for your question.

    The ALTPLL Bandwidth - Preset setting controls the PLL loop bandwidth. In practice, this is a tradeoff between filtering input-clock jitter and achieving faster lock time. In your case, the improvement after changing from "Auto" to "Low" suggests that input clock jitter or noise may be a factor, because the Low setting filters more reference-clock jitter. Based on this, personally I would keep "Low" setting unless you have a specific reason to prioritize faster lock time. I would not expect "Medium" settings to be better by default, because it provides less jitter filtering than "Low". You may check this and confirm back if possible.

    You can also check the reference clock quality and board-level jitter/noise.

    Reference:

    1. https://resources.altera.com/quartushelp/current/index.htm#logicops/logicops/def_pll_bandwidth.htm

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