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Honored Contributor
Honored ContributorAltmemddr_sysclk
Dear all, We all know we use altmemddr_sysclk a lot in SOPC builder for DDR SDRAM controller and to drive other SOPC module. There are so many clock, anyone can summarize their relationshi...
Altera_ForumHonored Contributor
Honored ContributorHere you go:
http://www.altera.com/literature/hb/external-memory/emi_ddr_ug.pdf The sysclk is the clock intended to be used for your parallel domain interface to the DDR SDRAM controller. This clock may be either 1X or 2X the phy clock depending on whether you've selected a Full-rate or Half-rate interface. The mem_clk (and mem_clk_n) signals are the actual physical layer clock(s) that connect to the DDR component(s) (or module(s)). Jake
