altlvds pll clock timing constraints

1) Yes. The multicycles and false paths loosen the default constraints. If these were critical paths, it can make a huge difference. If they weren't though, it might not help.

2) Depends. The general rule of thumb is that every clock that comes in on a different I/O port is a new domain. So if it feeds 2 PLLs, then that port clock plus all the generated clocks out of the two PLLs would be in the same group. If another clock comes in on another port and feeds another PLL, all of those would go in another group. There are cases where this doesn't hold true though. Sometimes the same board clock feeds two input ports, so they might be related. Sometimes a single PLL creates clocks that are not related(I have one that creates a 1x clock and a 25/19x clock), so they're in separate groups and I handle the domain crossing correctly(carefully).

3) Depends. What's causing the hold violation. There are many possibilities, so it's tough to say. In general, with edge aligned, related clocks, there will never be a hold violation because the clock edges hit the source and destination registers are approximately the same time. So something is causing your clocks to hit the source and destination at different times, like a gated clock on one of the clocks. There are plenty of other possibilities for this, so you really need to understand what the hold violation is telling you, why it's occuring, and make a plan of action from there.