Honored Contributor
Honored ContributorThanks for your help so far.
This is what I get (below) So I have three questions: 1) Does this help the fitter to achieve timing? 2) Should I keep all derived clocks in the same clock group? 3) If I get a hold violation, what, if anything, can I do about it? Info: Deriving PLL Clocks Info: create_generated_clock -source inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|inclk[0] -multiply_by 7 -phase -180.00 -duty_cycle 50.00 -name inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|clk[0] inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|clk[0] Info: create_generated_clock -source inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|inclk[0] -phase 257.14 -duty_cycle 14.00 -name inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|clk[1] inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|clk[1] Info: create_generated_clock -source inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|inclk[0] -phase -25.71 -duty_cycle 50.00 -name inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|clk[2] inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|pll|clk[2] Info: set_multicycle_path -setup -start 7 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_4|clk0]] Info: set_multicycle_path -hold -start 6 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_4|clk0]] Info: set_false_path -to [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_4|datain]] Info: set_multicycle_path -setup -start 7 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_5|clk0]] Info: set_multicycle_path -hold -start 6 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_5|clk0]] Info: set_false_path -to [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_5|datain]] Info: set_multicycle_path -setup -start 7 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_0|clk0]] Info: set_multicycle_path -hold -start 6 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_0|clk0]] Info: set_false_path -to [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_0|datain]] Info: set_multicycle_path -setup -start 7 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_1|clk0]] Info: set_multicycle_path -hold -start 6 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_1|clk0]] Info: set_false_path -to [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_1|datain]] Info: set_multicycle_path -setup -start 7 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_2|clk0]] Info: set_multicycle_path -hold -start 6 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_2|clk0]] Info: set_false_path -to [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_2|datain]] Info: set_multicycle_path -setup -start 7 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_3|clk0]] Info: set_multicycle_path -hold -start 6 -from [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_3|clk0]] Info: set_false_path -to [get_pins [list inst17|inter_processor_link_altlvds_rx_a|altlvds_rx_component|auto_generated|rx_3|datain]]
