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Altera_Forum
Honored Contributor
Honored Contributoraltlvds pll clock timing constraints
Hello, I'm getting a hold slack violation between clock outputs on the PLL used by an altlvds_rx module. clk0 output is 300MHz and clk2 is div 7 or 42.86. My question is, should I be includi...
Altera_ForumHonored Contributor
Honored ContributorThere's two issues:
1) Yes, these should be in separate groups, becasue there really is no constant relationshp between a 300MHz clock and a 42.8571428...MHz clock. So there's no way a hold or setup requirement could be correct. So yes, put them in separate groups. 2) In separate groups, TimeQuest will no longer do timing analysis between them, which is correct. Your design needs to now make sure they are treated in an asynchronous manner if passing data between the two domains. An asynch FIFO, a handshaking scheme, or something like that. Actually, there is another possibility. Your data may be "shaped" for this, i.e. your logic produced 7 bits of data that then need to be transferred to the 300Mhz domain on every 7th clock. Is that's what is going on? (I haven't answered exactly, but please provide more info based on that and we can probably figure it out. One last thing might be to try running derive_pll_clocks, and see what that does in its Info message, since I believe that constraints ALTLVDS PLLs too.)
