Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

ALTLVDS Failing timing on simple interface

Hi I am failing timing implementing a simple ALTLVDS The clock speed is 200MHz the de-serialization factor is 2. I am interfacing a CYCLONE V SOC system to a two channel, 14 bit ADC (ADS4249) A...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

--- Quote Start ---

Hi,

Why are you using ALTLVDS IP? In my opinion this IP is not suitable for your needs. If I were you a would use simple DDR input registers with PLL.

--- Quote End ---

Hi Thanks. I think you make complete sense. I will try ddrio. Cheers Dave