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Altera_Forum
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8 years ago

ALTLVDS Failing timing on simple interface

Hi I am failing timing implementing a simple ALTLVDS The clock speed is 200MHz the de-serialization factor is 2. I am interfacing a CYCLONE V SOC system to a two channel, 14 bit ADC (ADS4249) A...
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Altera_Forum
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8 years ago

Hi,

Why are you using ALTLVDS IP? In my opinion this IP is not suitable for your needs. If I were you a would use simple DDR input registers with PLL.