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Altera_Forum
Honored Contributor
16 years agoALTGX the cal_blk_clk signal, what is it?
Please help with a simple query. I set up a ALTGX using the wizard tool, the pll_inclk signal is the reference clock that is multiplied by PLL to make tx_clkout[0] and time the serial data righ...
Altera_Forum
Honored Contributor
16 years agoHello,
i want to know how much space it require for the WIN CE OS on a DDR? a)How much it requires for read/write in mobile DDR? Regards Vinoth.