ALTGX reconfiguration with multiple pll clock inputs Error (21113)

I have a design on Stratix IV with an ALTGX transceiver (tx only) which can operate at different frequencies. I use the reconfiguration mechanism (i.e. ALTGX RECONFIG) to be able to switch between the different HSIO frequencies.

For this purpose, the ALTGX pll_inclk_rx_cruclk port is fed by two clocks from a pll instance:

ALTGX INSTANCE:

fpga_transceiver i_fpga_transceiver(

...

.pll_inclk_rx_cruclk({w_fpga_pll_c1,w_fpga_pll_c2}), // input [1:0]

...

PLL INSTANCE:

fpga_pll i_fpga_pll(

.inclk0( SMA_CLKIN_p ),

.c0 (w_fpga_pll_c0), //

.c1 (w_fpga_pll_c1), // Clock for first HSIO freq

.c2 (w_fpga_pll_c2), // Clock for second HSIO freq

.locked (w_fpga_pll_locked)

);

The design does not compile, I have the following error:

Error (21113): Signal "fpga_pll:i_fpga_pll|altpll:altpll_component|fpga_pll_altpll:auto_generated|wire_pll1_clk[1]" feeds the inclk[1] input port of the GXB transceiver PLL "fpga_transceiver:i_fpga_transceiver|fpga_transceiver_alt4gxb:fpga_transceiver_alt4gxb_component|tx_pll0", but the HSSI PLL can have only 1 direct cascade path from GPLL clock

I would be most thankful if someone could help me fixing this issue!